1. Field of the Invention
The present invention relates to a semiconductor device such as a large scale integrated circuit (LSI) and, more particularly, to an element structure of an input protection circuit section.
2. Description of the Related Art
In general, elements in the chip of a semiconductor device such as an LSI are broken down when a high voltage accidentally applied to external terminals of the semiconductor device or ESD (ElectroStatic Discharge) occurs, i.e., static electricity charged in a human body is discharged to the external terminals. As a countermeasure against this, an input protection circuit is generally arranged to protect the elements in the LSI.
FIG. 1 shows an element structure of an input protection circuit section in a conventional LSI, e.g., a 1-Mbit dynamic random access memory (DRAM). In FIG. 1, reference numeral 21 denotes a p-type semiconductor substrate; 22, an n.sup.+ -type first semiconductor region (n.sup.+ -type diffusion layer) formed in a part of the surface region of the p-type substrate 21 and connected to an input pad 25 for receiving an external signal; and 23 and 24, n.sup.+ -type second semiconductor regions (n.sup.+ -type diffusion layers), formed in a part of the surface region of the p-type substrate 21, for receiving a ground potential Vss. An input circuit section (not shown) of the LSI is connected to the input pad 25.
FIG. 2 shows an equivalent circuit of the input protection circuit section shown in FIG. 1. In FIG. 2, reference numeral 26 denotes a resistor component between the input pad 25 and the n.sup.+ -type diffusion layer 22, and the reference numeral 27 denotes a parasitic bipolar transistor (npn transistor) formed by the n.sup.+ -type diffusion layer 22, the p-type substrate 21, and the n.sup.+ -type diffusion layers 23 and 24. The base potential of the parasitic bipolar transistor 27 is equal to the potential of the substrate 21, and a back gate bias potential V.sub.BB is normally given as this potential.
In the input protection circuit section having the above arrangement, when a high voltage is accidentally applied to an external terminal (not shown) connected to the input pad 25 or electrostatic discharge occurs, an overcurrent flows from the n.sup.+ -type diffusion layer 22 connected to the input pad 25 to the n.sup.+ -type diffusion layers 23 and 24 to prevent breakdown of circuit elements in the LSI.
The base potential of the parasitic bipolar transistor 27 is equal to the back gate bias potential V.sub.BB, and the back gate bias potential V.sub.BB is used in a transistor of a memory cell array section or cell peripheral circuit section (not shown) arranged on the semiconductor substrate 21. For this reason, when an overcurrent flows from an external terminal (not shown) to the input pad 25 due to electrostatic discharge, a large amount of current flows to the semiconductor substrate 21 to cause the substrate potential to be unstable, and the transistors of the memory cell array section or cell peripheral circuit section may be broken down.
In a test for an integrated circuit, a predetermined negative potential (V.sub.IL) is applied to an external terminal (not shown) connected to the input pad 25. At this time, minority carriers generated by the n.sup.+ -type diffusion layer 22 connected to the input pad 25 flow into the semiconductor substrate 21 to cause the back gate bias potential V.sub.BB to be unstable. For this reason, in other sections except for the input protection circuit section, a transistor using the back gate bias potential V.sub.BB may be erroneously operated.